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   <div id="projectname">CMSIS-Core (Cortex-M)
   &#160;<span id="projectnumber">Version 5.6.0</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="title">Reference</div>  </div>
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<div class="contents">
<div class="textblock">Here is a list of all modules:</div><div class="directory">
<div class="levels">[detail level <span onclick="javascript:toggleLevel(1);">1</span><span onclick="javascript:toggleLevel(2);">2</span>]</div><table class="directory">
<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__device__config.html" target="_self">Device capabilitiy defines</a></td><td class="desc">Defines to configure and check device capabilities </td></tr>
<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__version__control__gr.html" target="_self">Version Control</a></td><td class="desc">Version #define symbols for CMSIS release specific C/C++ source code </td></tr>
<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__compiler__conntrol__gr.html" target="_self">Compiler Control</a></td><td class="desc">Compiler agnostic #define symbols for generic C/C++ source code </td></tr>
<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__peripheral__gr.html" target="_self">Peripheral Access</a></td><td class="desc">Naming conventions and optional features for accessing peripherals </td></tr>
<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__system__init__gr.html" target="_self">System and Clock Configuration</a></td><td class="desc">Functions for system and clock setup available in system_<em>device</em>.c </td></tr>
<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__NVIC__gr.html" target="_self">Interrupts and Exceptions (NVIC)</a></td><td class="desc">Functions to access the Nested Vector Interrupt Controller (NVIC) </td></tr>
<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__Core__Register__gr.html" target="_self">Core Register Access</a></td><td class="desc">Functions to access the Cortex-M core registers </td></tr>
<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic__CPU__gr.html" target="_self">Intrinsic Functions for CPU Instructions</a></td><td class="desc">Functions that generate specific Cortex-M CPU Instructions </td></tr>
<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic__SIMD__gr.html" target="_self">Intrinsic Functions for SIMD Instructions</a></td><td class="desc">Access to dedicated SIMD instructions available on Armv7E-M (Cortex-M4/M7), Armv8-M Mainline (Cortex-M33/M35P), and Armv8.1-M (Cortex-M55/M85) </td></tr>
<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__fpu__functions.html" target="_self">FPU Functions</a></td><td class="desc">Functions that relate to the Floating-Point Arithmetic Unit </td></tr>
<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__mve__functions.html" target="_self">MVE Functions</a></td><td class="desc">Functions that relate to the MVE (Cortex-M Vector Extensions) Unit </td></tr>
<tr id="row_11_"><td class="entry"><img id="arr_11_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('11_')"/><a class="el" href="group__mpu__functions.html" target="_self">MPU Functions for Armv6-M/v7-M</a></td><td class="desc">Functions that relate to the Memory Protection Unit </td></tr>
<tr id="row_11_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__mpu__defines.html" target="_self">Define values</a></td><td class="desc">Define values for MPU region setup </td></tr>
<tr id="row_12_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__mpu8__functions.html" target="_self">MPU Functions for Armv8-M</a></td><td class="desc">Functions that relate to the Memory Protection Unit </td></tr>
<tr id="row_13_" class="even"><td class="entry"><img id="arr_13_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('13_')"/><a class="el" href="group__pmu8__functions.html" target="_self">PMU Functions for Armv8.1-M</a></td><td class="desc">Functions that relate to the Performance Monitoring Unit </td></tr>
<tr id="row_13_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__pmu8__events__armv81.html" target="_self">PMU Events for Armv8.1-M</a></td><td class="desc">IDs for Armv8.1-M architecture defined events </td></tr>
<tr id="row_13_1_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__pmu8__events__armcm55.html" target="_self">PMU Events for Cortex-M55</a></td><td class="desc">IDs for additional events defined for Cortex-M55 </td></tr>
<tr id="row_13_2_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__pmu8__events__armcm85.html" target="_self">PMU Events for Cortex-M85</a></td><td class="desc">IDs for additional events defined for Cortex-M85 </td></tr>
<tr id="row_14_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__SysTick__gr.html" target="_self">Systick Timer (SYSTICK)</a></td><td class="desc">Initialize and start the SysTick timer </td></tr>
<tr id="row_15_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__ITM__Debug__gr.html" target="_self">Debug Access</a></td><td class="desc">Debug Access to the Instrumented Trace Macrocell (ITM) </td></tr>
<tr id="row_16_" class="even"><td class="entry"><img id="arr_16_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('16_')"/><a class="el" href="group__trustzone__functions.html" target="_self">TrustZone for Armv8-M/v8.1-M</a></td><td class="desc">Functions that related to optional Armv8-M and Armv8.1-M security extension </td></tr>
<tr id="row_16_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__coreregister__trustzone__functions.html" target="_self">Core Register Access Functions</a></td><td class="desc">Core register Access functions related to TrustZone for Armv8-M </td></tr>
<tr id="row_16_1_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__nvic__trustzone__functions.html" target="_self">NVIC Functions</a></td><td class="desc">Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M </td></tr>
<tr id="row_16_2_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__systick__trustzone__functions.html" target="_self">SysTick Functions</a></td><td class="desc">SysTick functions related to TrustZone for Armv8-M </td></tr>
<tr id="row_16_3_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__sau__trustzone__functions.html" target="_self">SAU Functions</a></td><td class="desc">Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M </td></tr>
<tr id="row_16_4_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__stacksealing__support__trustzone__functions.html" target="_self">Stack Sealing Support Functions</a></td><td class="desc">Stack sealing macros and helper functions </td></tr>
<tr id="row_16_5_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__context__trustzone__functions.html" target="_self">RTOS Context Management</a></td><td class="desc">RTOS Thread Context Management for Armv8-M TrustZone </td></tr>
<tr id="row_17_"><td class="entry"><img id="arr_17_" src="ftv2mlastnode.png" alt="\" width="16" height="22" onclick="toggleFolder('17_')"/><a class="el" href="group__cache__functions__m7.html" target="_self">Cache Functions (Level-1)</a></td><td class="desc">Functions for level-1 instruction and data cache </td></tr>
<tr id="row_17_0_" class="even"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__Icache__functions__m7.html" target="_self">I-Cache Functions</a></td><td class="desc">Functions for the level-1 instruction cache </td></tr>
<tr id="row_17_1_"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__Dcache__functions__m7.html" target="_self">D-Cache Functions</a></td><td class="desc">Functions for the level-1 data cache </td></tr>
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